Integrated memories, for example, in the form of DRAMs (dynamic random access memories), are generally subject to comprehensive functional tests in the fabrication process. Inter alia, the functional tests identify defective memory cells or defective column lines or row lines. As memory size increases, the costs of functional tests make up an ever greater proportion of the overall production costs of a memory. In order to lower the test costs, however, methods such as test modes for compressing data or additional test logic, for example, in the form of BIST (built-in self-test), are increasingly being developed.
Integrated memories generally have redundant memory cells for repairing defective memory cells. The redundant memory cells are usually combined to form redundant row lines or redundant column lines that can replace regular lines having defective memory cells in address terms. As a result, integrated memories, in particular, DRAMs, are still fabricated economically with the integration densities that are achieved nowadays. An integrated memory is tested, for example, by an external test device and a programming of redundant elements is subsequently performed based on a redundancy analysis. In order to be able to carry out a repair of a memory in a targeted manner, it is necessary, in corresponding tests or test sequences, to identify defects and store them together with the associated address on the external test system. The addresses of those tested memory cells, which have been detected as defective, are stored in a defect address memory, i.e., fail bit map, in order to replace these memory cells by defect-free redundant memory cells in a subsequent step on the basis of the stored addresses. The repair solution specific to each memory can subsequently be calculated in the test system based on the fail bit map.
In order to minimize the test costs per memory chip, the memory chips are tested in parallel to an increasing extent. This trend is supplemented by the increasing use of test circuits that are provided on the memory chip, such as, for example, circuits for carrying out built-in self-tests (BIST) or compression test modes. Such circuits support an externally connected test unit for functional testing of the memory chip. With the use of a BIST, the test control (address and data generation, command sequence) is generally effected completely in the memory chip.
Increasingly problematical is that the calculation of the repair solution upon establishing functional defects in the memory chip still must be effected externally. Therefore, it is necessary to transmit the redundancy-conforming defect data to an external unit even in the case of a BIST-based test cycle. The external unit receives the defect data and calculates a repair solution therefrom. In the case of a high degree of parallelism and in the case of high storage densities, such as are achieved in the present-day state of development, such transmission poses a problem for a number of reasons. First, the defect data can be transmitted in highly parallel fashion from each individual memory chip. This requires a correspondingly high number of expensive connection channels at the external test system or data acquisition system. Furthermore, the wiring on the load boards of the test systems may become very complex. An alternative to this is to reduce the number of output lines per memory chip to be tested and to transmit the addresses of the defect data identified in the chip serially to the external test unit. However, this requires correspondingly more test time and thus likewise leads to raising test costs.